MATLAB SIMULINK HDL CODER 1 Bedienungsanleitung PDF herunterladen (Seite 24)

9/21/2011

24

Demo: HDL Workflow Advisor

Create FPGA project

Run P&R

-and-

Annotate timing information

52

Automated workflow 

from model to FPGA Analysis &

Implementation

Identifying the critical path

Speed Optimization

53

Critical Path highlighting:

 Visual representation of critical path in your model

 Easier to identify bottlenecks of your model

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